JLCPCB production package · pre-order review

HDMI Controller Fab Review

The Gerber, drill, BOM and pick-and-place files are complete and inside JLCPCB's 4-layer rules. Four schematic-level defects would make the assembled board unflashable or unusable, and each is a few cents to fix now and a re-spin later.

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to order4 blockers · 7 to confirm

Export: ProPrj_HDMI_Controller1 · 2026-09-04 · Gerber set 2026-09-05
Reviewed: 2026-09-08, from the raw files (netlist rebuilt from the flying-probe JSON, Gerbers parsed, BOM reconciled), then every finding independently re-derived
Board: 65.00 × 50.00 mm · 4 layers · 1.6 mm assumed
Parts: 69 BOM lines · 154 placed parts · 138 top / 16 bottom · 4 JST-XH headers through-hole
Processor: ESP32-P4NRW32X (U3) + ESP32-C6-MINI-1U (U5), nRF24L01+ (U12)

Blockers — fix before ordering

Each of these was checked against the netlist in the export, the ESP32-P4 datasheet (v0.7), Espressif's hardware design guidelines and their ESP32-P4-Function-EV-Board schematic, and the vendor pages of the parts named.

GPIO36 is floating, so the board cannot enter download mode

What the files say

U3 pin 68 (GPIO36) is a single-pin net (NET_64) — no resistor, no capacitor, nothing. Pins 69 and 70 (GPIO37/GPIO38, UART0) are single-pin nets as well.

The datasheet's Table 3-1 gives GPIO36 no internal pull ("Floating"). Table 3-3 requires GPIO35 = 0 and GPIO36 = 1 for joint download boot; esptool's boot-mode page adds that GPIO35 = 0 with GPIO36 = 0 "is invalid and will trigger unexpected behavior". Espressif's own EV board routes GPIO36 to a GPIO36_BOOTMODE net with a 10 kΩ pull-up (R209).

Why it blocks

The W25Q flash arrives blank from JLCPCB. Every first-program path — DFU over USB-C, esptool over USB-Serial-JTAG, UART — needs the ROM in download mode, which this strap cannot reliably reach. The only remaining route is OpenOCD through the USB-Serial-JTAG test pads.

Fix

Add one 0402 10 kΩ from U3 pin 68 to +3V3. GPIO36 is "any value" in normal SPI boot, so the pull-up costs nothing at run time.

L5 saturates at 60 mA on a rail that needs at least 380 mA

What the files say

BOM line 33: L5 = TDK MLZ1005M2R2WT000 (LCSC C383389) in an L0402 footprint. In the netlist L5 sits between VDD-HP and U15 pin 3, the SW pin of the TLV62569 core buck.

TDK lists that part in its "inductors for decoupling circuits" series: 2.2 µH, 60 mA saturation current (the binding maximum, where inductance has fallen 50 %), 350 mA only as a 20 °C temperature-rise reference, DCR 0.55 Ω typical and 0.715 Ω maximum. It is a multilayer ferrite, not a power inductor. Espressif's schematic checklist puts the chip's minimum operating supply current at 380 mA (3.3 V input, including flash and PSRAM) and defers inductor ratings to the regulator datasheet; TI's TLV62569 datasheet asks for a saturation rating 20–30 % above peak inductor current and uses a 4 × 4 mm power inductor as its example.

Why it blocks

With the core drawing a few hundred milliamps at 1.1 V, peak inductor current works out near 0.6 A — ten times L5's saturation rating. The inductance collapses, ripple current climbs to the TLV62569's limit, and the 0402 dissipates on the order of 100 mW in its own DCR. The core rail will be noisy at best and brown out under load at worst.

Fix

A 2.2 µH power inductor with a saturation rating of 1 A or more. The simplest choice is the YHNR4020-2R2M already fitted at L1 on the 3.3 V rail (4 A rated, 6 A saturation, 46 mΩ; the same 4 × 4 mm class as TI's reference example) — or a smaller part such as Murata DFE201610E-2R2M (2.0 × 1.6 mm) if space is tight. Either needs a footprint change. Nothing else in the buck needs touching: TLV62569, R78/R79 499 kΩ, C30 22 pF, C31 22 µF and C29 4.7 µF are exactly the values in Espressif's TLV62569 reference for chip revision v3.0 and later.

U17 is an 8 MB flash; the firmware's partition table needs 12.4 MB

What the files say

BOM line 68: U17 = W25Q64JVSSIQ (LCSC C2904572, SOP-8 208 mil). It is the P4's flash: pin 8 is on VDD-FLASH with U3 pins 30 and 71, and its D/Q lines reach U3 pins 33 and 28.

The firmware's partitions.csv ends at 0xC60000 — two 4 MB OTA slots, a 4 MB storage partition and NVS — which does not fit 8 MB.

Why it blocks

The current image cannot be flashed to this board at all. Shrinking the table is possible but gives up the second OTA slot on the chip that is the only update path for the C6.

Fix

Winbond W25Q128JVSIQ (16 MB, LCSC C97521, same SOIC-8 208 mil footprint, 38 k in stock on 2026-09-08) or W25Q256JVEIQ (32 MB, same as the devkit). The flash pull-up R51 already references VDD-FLASH, which is correct.

The IR-receive jack puts the receiver's supply on a sleeve contact, which any plug shorts to ground

What the files say

CN1 and CN2 are SHOU HAN PJ-327A 5JJ (LCSC C668605). The manufacturer's drawing for this exact part (dated 2020-06-24) shows the contact functions: pins 1 and 2 are both the sleeve (two phosphor-bronze springs on the plug body), pin 3 is the ring, pin 4 is the tip (stainless spring) and pin 5 is a normally-closed switch contact that rests on pin 4 until a plug lifts it. Contact depths from the board edge are 1.7 / 2.7 / 5.4 / 9.7 / 11.4 mm, and the export's pads sit at exactly those positions. The nets on them:

Pin	Contact	CN1 (IR transmit)	CN2 (IR receive)
1	Sleeve · 1.7 mm	GND	GND
2	Sleeve · 2.7 mm	GND	+3V3 via R86 47 Ω (receiver Vcc, C77/C78 filter)
3	Ring · 5.4 mm	Insertion detect → R85 1 k → GPIO49 (R84 10 k pull-up)	Signal → R90 1 k → GPIO50 (R89 10 k pull-up)
4	Tip · 9.7 mm	LED feed: VBUS → Q7 → R80 33 Ω (D6 ESD)	Detect → R88 1 k → GPIO27 (R87 10 k pull-up, D7 ESD)
5	Tip switch (NC to 4) · 11.4 mm	unconnected	unconnected

CN1 is wired correctly: LED drive on the tip, return on the sleeve, and the ring as insertion detect (a mono TS plug's long sleeve shorts the ring contact to ground; a TRS plug would not trigger it).

Why it blocks

CN2 pin 2 is a sleeve contact. With any plug inserted, the receiver's 3.3 V supply is shorted to ground through R86: 70 mA continuously, 0.23 W in a 0603 resistor rated for 0.1 W, and 0 V at the receiver. With no plug, nothing happens, so the fault only appears in use.
Nothing else on CN2 can power a receiver either: the ring is the signal input (10 kΩ pull-up) and the tip is a sense line through 10 kΩ. As drawn, the IR-receive zone cannot work with any cable.

Fix

Keep both sleeve pins on GND. Put the receiver's Vcc (R86 + C77/C78) and its signal on the ring (pin 3) and tip (pin 4) in whichever order the receiver cable uses — the common IR-receiver convention is tip = signal, ring = +V. For insertion detect, use pin 5: it rests on the tip when the jack is empty and opens when a plug is in, so a pull-down on pin 5 with R88/D7 gives a clean present/absent level on GPIO27 (the current pull-up on pin 4 would then be removed). This closes the open item in BOM.md §4.

Confirm before ordering

None of these stops JLCPCB from building the board. Each one decides whether the board that arrives can be brought up, and two of them (pull-ups, antenna) are cheaper to settle in this revision than the next.

The main processor is out of stock at LCSC

Status: U3 C54540373 (ESP32-P4NRW32X, QFN-104) showed "out of stock — notify me" on LCSC on 2026-09-08. JLCPCB assembly draws from that inventory. Check again at order time, or arrange a consigned/pre-ordered part. U5 C20627095 (ESP32-C6-MINI-1U-H4) had 411 in stock the same day.

The C6 module has no antenna

Status: U5 is ESP32-C6-MINI-1U-H4, the external-antenna variant with an MHF3 (IPEX-3) socket. No pigtail, antenna or matching connector appears in the BOM, and RF2 (2337019-1) is the nRF24's chip antenna, wired into its L2/L3/L4 match. As shipped, the C6 — Wi-Fi and BLE — is deaf.
Decide: Either add an MHF3 pigtail + antenna to the kit (and the enclosure), or swap to ESP32-C6-MINI-1-H4 with the PCB antenna — same footprint, but the antenna end then needs a copper keep-out in the layout.

The P4–C6 link is four wires: it can be SDIO 1-bit, not esp-hosted SPI

What the files say

P4 pin	P4 GPIO	Series R	C6 module pin	C6 GPIO	SDIO function	Net label in export
7	GPIO7	R9 22 Ω	24	IO18	SDIO_CMD	P4_CS
8	GPIO8	R10 22 Ω	25	IO19	SDIO_CLK	P4_MOSI
10	GPIO9	R11 22 Ω	26	IO20	SDIO_DATA0	P4_SCLK
11	GPIO10	R16 22 Ω	27	IO21	SDIO_DATA1	P4_MISO
98	GPIO54	R77 220 Ω	8	EN	slave reset	NET_4

No other C6 IO reaches the P4. esp-hosted's SPI transport (full- or half-duplex) needs a handshake and a data-ready line from the C6, so it cannot run on this wiring. esp-hosted's SDIO 1-bit mode can: the four lines land exactly on the C6's SDIO CMD/CLK/D0/D1, the P4's SDMMC host routes through the GPIO matrix, the C6 firmware already runs as an SDIO slave, and the reset GPIO matches the devkit configuration.

Gap

There are no pull-ups on the four lines. SDIO needs 10–51 kΩ on CMD and every DAT line; the C6 firmware's own comment says its internal pull-ups "are not sufficient". Add three 0402 10 kΩ (CMD, D0, D1) to +3V3 in this revision. IO22/IO23 (D2/D3) are unconnected and can stay on the C6's internal pull-ups in 1-bit mode.

Firmware

P4: ESP_HOSTED_SDIO_1_BIT_BUS, CMD 7 / CLK 8 / D0 9 / D1 10, reset 54. C6: unchanged (SDIO slave). Expect roughly a quarter of the devkit's 4-bit throughput, which is ample for this device.

USB-C lands on the high-speed OTG pins: DFU works, the console does not

What the files say

USBC1 D+/D− → D1 (USBLC6-2SC6) → U3 pins 50/49, which the datasheet names USB_DP/USB_DM: the dedicated USB 2.0 High-Speed OTG PHY on VDD_USBPHY (pin 51, on +3V3). Datasheet §3.1: "USB 2.0 OTG Download Boot (only the USB 2.0 High-Speed OTG can be used for flashing…)", so ROM DFU over this connector is supported once B1 is fixed.

USB-Serial-JTAG (GPIO24/GPIO25, pins 52/53) goes only to test pads DM1/DP1. UART0 (GPIO37/GPIO38) is unconnected; the U19 header carries GPIO14/GPIO15, which the application can use as a UART but the ROM cannot.

Consequence

The firmware's serial console (USB-Serial-JTAG on the devkit) will be silent on this board. Options: add a TinyUSB CDC console on the OTG port in firmware, or wire a cable to DM1/DP1 for the bench. The pad-JTAG header U13 (P4 pins 2–5) is inert with blank eFuses — the P4 defaults JTAG to USB-Serial-JTAG; using U13 needs JTAG_SEL_ENABLE burned with GPIO34 low at reset, and GPIO34 is the nRF24 CE line with no pull.

Small layout items JLCPCB will accept but you may not want

List

Two open U-shaped strokes from the CN1/CN2 jack footprints sit on the board-outline layer and hang 0.35 mm past the left edge (x 319.53–319.91 mm). They are not part of the profile; delete them from the outline layer so the CAM engineer does not have to guess.
21 top-silk segments are 0.10–0.127 mm wide (JLCPCB minimum 0.15 mm); they will print thin or drop out. The rest of the silk is 0.15–0.254 mm.
The USB-C B-row through-hole pads have a 0.10 mm annular ring on a 0.40 mm drill — the stock LCSC footprint for TYPE-C-31-M-04, widely fabbed, but below JLCPCB's recommended 0.15 mm.
The four M2 mounting holes are in the plated-hole file with a 2.0 mm copper pad on a 2.0 mm drill (zero annulus). If they are meant to be non-plated, move them to the NPTH file.
The two status LEDs use different series resistors: R48 1 kΩ, R49 2.2 kΩ. Intentional brightness match, or a leftover?

The IR zone works only after B4 — but its circuit is otherwise sound

Verified: Transmit: GPIO26 → R83 4.7 kΩ → Q8 (MMBT3904, R82 100 kΩ base pull-down) → Q7 (AO3401A high-side from VBUS, R81 100 kΩ) → R80 33 Ω 1206 → jack, with D6 5 V ESD. Receive: supply from +3V3 through R86 47 Ω with C77/C78 filtering (the "no DC supply" defect from the Aug-15 review is fixed), signal with 10 kΩ pull-up and 1 kΩ series into GPIO50, insertion detect on GPIO49 (TX) and GPIO27 (RX) with 3.3 V ESD.

The design documents describe the August board, not this one

Status: BOM.md, GPIOs.md, Rework.md and the schematic PDF are the 2026-08-15 revision. This export renumbered references: U13 is now the P4 JTAG header (the flash is U17), R11 is a 22 Ω SDIO series resistor (the 27 kΩ CEC pull-up is R62), the R31–R36 SDIO pull-ups are gone, and the four jacks became two. Regenerate the docs from the corrected schematic so the next review starts from the right names.

What passed

Every number below was recomputed from the files in the export, not read from the EasyEDA report.

Check	Result	Evidence
Package contents	Pass	Gerber RS-274X: 4 copper, mask/paste/silk both sides, outline, document layer; Excellon PTH, NPTH and via files; BOM.xlsx and PickAndPlace.xlsx in JLCPCB column format; the zip matches the folder byte for byte.
Outline and stack	Pass	65.00 × 50.00 mm closed rectangle, 4 layers; inner layers 1 and 2 are solid planes with 0.257 mm edge pull-back.
Trace and space	Pass	Smallest copper draw aperture 0.15 mm on the top layer, 0.20 mm on the bottom; the inner layers carry only pads and planes. JLCPCB 4-layer minimum 0.09 mm (1 oz).
Drills and rings	Pass	Smallest drill 0.20 mm (JLCPCB minimum 0.15); via rings ≥ 0.125 mm; drill sizes 0.2 / 0.25 / 0.3 / 0.4 / 0.6 / 0.7 / 0.8 / 1.0 / 1.1 / 2.0 mm.
Copper to edge	Pass	0.257 mm minimum on all four copper layers (JLCPCB ≥ 0.20 mm).
Solder paste	Pass	All 532 top and 32 bottom SMD pads have paste (flashes plus region fills); U3 exposed pad 7.5 × 7.5 mm has a 6 × 6 mm window (64 %); HDMI1 pins 1–19 pasted.
BOM ↔ pick-and-place	Pass	69 BOM lines ↔ 154 placed parts, no orphans either way; the 11 extra pick-and-place rows are the 7 test points and 4 screw holes, which correctly have no BOM line; every BOM line carries a JLCPCB/LCSC C-code.
Assembly type	Pass	138 parts on top, 16 on the bottom (15 capacitors + R76) → order Standard assembly, not Economic (single-side).
Straps and resets	Pass	BOOT on GPIO35 (10 kΩ + internal pull-up, 100 nF); EN 10 kΩ / 1 µF as Espressif recommends; C6 EN 10 kΩ + 100 nF, reset from GPIO54 via 220 Ω; C6 BOOT 10 kΩ.
Core DC-DC topology	Pass	TLV62569 driven by EN_DCDC (pin 79) and FB_DCDC (pin 78), 499 kΩ / 499 kΩ / 22 pF / 22 µF / 4.7 µF — identical to Espressif's TLV62569 reference for chip revision v3.0 and later (Fig. 5 of the design guidelines), the right one for the P4NRW32X; the EV board leaves those three feedback parts unfitted because it was drawn for v1.x silicon. Only the inductor's rating departs from the reference (B2). VDD_HP decoupled at all four pins; VDD_USBPHY and VDD_ANA (via L6 ferrite) on +3V3.
HDMI and CEC	Pass	Full-size Type A (C2858275); pin 13 CEC, 15/16 DDC through PCA9306 with 4.7 kΩ both sides, 17 GND, 18 +5 V (AZC199 ESD), 19 HPD → Q9 inverter → GPIO47. CEC: 27 kΩ pull-up through BAT54 to +3V3, 100 Ω series to GPIO40, AZ5123 TVS (the clamp deleted in August is back).
Flash and USB wiring	Pass	Flash VCC and its CS pull-up both on VDD-FLASH; USB-C CC pull-downs 5.1 kΩ; USBLC6-2SC6 on the high-speed pair; pair routed at 0.20 mm (impedance not controlled — acceptable for a few centimetres).

Pin map used in this review

ESP32-P4 QFN-104 package pins, translated with the datasheet pin table. Anything not listed is power, ground, crystal or unused.

Pin	GPIO	Net	Role on this board
2–5	MTCK/MTDI/MTMS/MTDO	P4_TCK…P4_TDO	U13 pad-JTAG header (inert until eFuse, see C4)
7, 8, 10, 11	GPIO7–GPIO10	P4_CS / MOSI / SCLK / MISO	C6 link = SDIO CMD / CLK / D0 / D1 (C3)
15, 16	GPIO14, GPIO15	RXD, TXD	U19 4-pin header (application UART)
25, 88	GPIO23, GPIO46	SDA, SCL	DDC via PCA9306
49, 50	USB_DM, USB_DP	USB_D−, USB_D+	USB-C through USBLC6 (HS OTG, C4)
52, 53	GPIO24, GPIO25	—	USB-Serial-JTAG, test pads DM1/DP1 only
55, 56	GPIO26, GPIO27	—	IR TX drive (Q8 base), IR RX insertion detect
65	GPIO34	CE	nRF24 CE (also the JTAG-source strap, floating)
66	GPIO35	NET_1	BOOT button, R25 10 kΩ, C15
68	GPIO36	NET_64	floating — B1
69, 70	GPIO37, GPIO38	—	UART0 TX/RX, unconnected
78, 79	FB_DCDC, EN_DCDC	FB-DCDC, EN-DCDC	TLV62569 FB and EN
80	GPIO39	IRQ	nRF24 IRQ
81	GPIO40	—	CEC via R95 100 Ω
82	GPIO41	FSW	function switch
89	GPIO47	HPD_DET	HPD, inverted by Q9
92, 93	GPIO49, GPIO50	—	IR TX insertion detect, IR RX signal
98	GPIO54	—	C6 reset via R77 220 Ω
103	CHIP_PU	EN	EN button, R76 10 kΩ, C69 1 µF

Sources

Export under review: board/electronic-schema/ProPrj_HDMI_Controller1_2026-09-04_Production File — Gerbers, drills, FlyingProbeTesting.json (netlist), BOM.xlsx, PickAndPlace_PCB1_2026_09_05.xlsx.
JLCPCB PCB capabilities — 4-layer trace/space, drill, ring, edge-clearance and silkscreen limits.
ESP32-P4 Series Datasheet v0.7 — pin table (§2), strapping pins and boot modes (§3, Tables 3-1 and 3-3).
ESP32-P4 schematic checklist — external DC-DC for VDD_HP, 380 mA minimum, verified regulators, Fig. 5 TLV62569 circuit for chip revisions v3.0+, EN RC values.
esptool: ESP32-P4 boot mode selection — GPIO35/GPIO36 requirement and the invalid (0, 0) combination.
ESP32-P4-Function-EV-Board schematic (v1.5.2) — GPIO36_BOOTMODE 10 kΩ pull-up (R209, sheet 3); its TLV62569 circuit leaves the feedback parts unfitted (v1.x silicon), so the v3.0+ figure in the design guidelines is the reference used here.
TI TLV62569 datasheet — inductor selection (saturation rating 20–30 % above peak current; 4 × 4 mm example part).
ESP-IDF: configure other JTAG interfaces (ESP32-P4) — default JTAG source and the GPIO34 / JTAG_SEL_ENABLE rule.
ESP32-C6-MINI-1 / MINI-1U datasheet — module pin 24–27 = IO18–IO21 (SDIO CMD/CLK/DATA0/DATA1).
TDK MLZ1005M2R2WT000 (LCSC C383389); Winbond W25Q128JVSIQ (C97521); ESP32-P4NRW32X (C54540373); PJ-327A 5JJ (C668605) with its manufacturer drawing and contact diagram; YHNR4020-2R2M (C2926400).
esp-hosted host Kconfig (local copy) and ESP-IDF v6.0.2 soc_caps.h for ESP32-P4 — SDIO 1-bit option and GPIO-matrix routing; C6 slave firmware sdio_slave_api.c pull-up note.